In a memory circuit, a weak memory cell refers to a memory cell having a cell current that is determined as the worst read margin among the memory cells of the memory circuit. In some applications, based on a statistical analysis of cell currents of the memory cells, the weak memory cell is determinable as the memory cell corresponding to a predetermined multiple of standard deviations less than an average cell current (e.g., −3σ, −4σ, −5σ or −6σ, etc.). In a read operation, a tracking signal is generated to provide a signal indicating a waiting period sufficient for a successful read operation of the weak memory cell. The waiting period is thus also applicable to reading other memory cells having cell currents greater than that of the weak memory cell.